Grinding the wafer backside by wheel to achieve the required thickness
· 8 inch,12 inch wafer processing capability
· Wafer grinding thickness can reach 30um
· Wafer grinding thickness error range ±5um
Wafer chipping is reduced by cutting the metal layer on the wafer surface by laser burning at high temperature
· Laser grooving width range 5-~35um
· Laser grooving thickness range 15~20um
Using a blade to cut the wafer in sequence
· The minimum cutting width can reach 40um
Die is attached to the substrate and secured by DAF
· Die bonding precision ±5um
· Double bond head improve efficiency
· Bonding die thickness of 30um, be able to stack 16 Die
The pad of the die is connected to the finger ofthe substrate by gold wireor alloy wire
· Minimum 0.6mil diameter gold wire
· Automatic focus, can work on multiple layers of products
Die and wire is sealed with compound, protect die and wire from damage,contamination and oxidation
· High precision equipment can produce 2-16 layers stacking
· It can reduce the rupture of ultra-thin chips, ensure the stabilityof the product quality.
The brand name and product information are marked onto the surface of the product by laser
· Depth error range ±3um
· One click to switch the product type
Solder ball bond onto the pad of the substrate
· Minimum diameter of solder ball 0.25mm
· Minimum spacing between solder balls
Using a blade to separate the die from the substrate
· Sawing width 0.2~0.3mm
· Sawing error range ±3um
The appearance of the product is tested through an optical lens, atthe same time, the equipment distinguishes the appearance type
· Solder ball appearance check
· Marking content check
Die and wire is sealed with compound, protect die and wire from damage,contamination and oxidation
· Automatic machine with vacuum system
· Automatic focus, can work on multiple layers of products
Basic Performance Test
Performance Test
IOPS Test
Latency Test
Customer Scenario Simulation Test
Raid Test
HAST HTOL LTOL
TC ELFT EDR
Read Interference Test
Data Retention Test
Lifetime Test
Compatibility test for different chipsets
compatibility test for different systems such as Window/Linux/Android and different versions
OS/Leakage Test
Static/Dynamic Power Consumption Test
AC Parameter Test
DC Parameter Test
Reference to JEDEC corresponding specification and corresponding protocol specification for complete protocol testing
SI signal integrity test
PI power integrity test
Stress test Power-down test
Hot-swap test Drop test
Upper and lower storage temperature limit test
Temperature bias quadrangle test
Temperature cycling test Temperature shock test
Operating temperature test High and low temperature read/write test,
Vibration test Shock test